1. Field of Invention
This invention relates in general to a manufacturing method for connecting transistors in a static random access memory (SRAM) component, and, more particularly, to a method for forming a poly-via connection between the drain of a load transistor and the gate of a driver transistor in a SRAM component.
2. Description of Related Art
FIG. 1 shows the circuit layout of a SRAM unit 10. A SRAM unit consists of a first driver transistor Q1 and a second driver transistor Q2, which are both enhancement mode N-type metal-oxide-semiconductor (NMOS) transistors. The source terminal 12 of the driver transistor Q1 and the source terminal 14 of driver transistor Q2 are connected to a reference ground voltage source Vss, the drain terminal 16 of Q2 and the gate terminal 18 of Q1 are connected together, and similarly the drain terminal 20 of Q1 and the gate terminal 22 of Q2 are connected together. The SRAM unit 10 in FIG. 1 also includes two load transistors Q3 and Q4, which are for the prevention of charge leakages from the drains 16 and 20 of the driver transistors Q1 and Q2 respectively, and therefore the load can actually be either a polysilicon resistor or a PMOS device. In order to reduce the dimensions of a SRAM unit 10 so as to expand its field of applications, the level of integration must be increased while its standby current must be reduced. Hence, the load transistors Q3 and Q4, for example, are P-type thin film transistors (TFT) with their source terminals 24 and 26 connected together and to a reference voltage Vcc, and their drain terminals 28 and 30 connected to the drain terminal 20 of Q1 and the drain terminal 16 of Q2 respectively, while their gate terminals 44 and 46 are connected to the gate terminal 18 of Q1 and gate terminal 22 of Q2 respectively.
The SRAM unit 10 of FIG. 1 further includes two enhancement mode NMOS devices Q5 and Q6 which act as transfer transistors. The gate terminals 32 and 34 of both Q5 and Q6 are connected to a word line labelled WORD, the source terminals 36 and 38 of Q5 and Q6 are connected to bit lines labelled BIT and bar BIT, respectively, while the drain terminals 40 and 42 of Q5 and Q6 are connected to the drain terminal 20 of Q1 and the drain terminal 16 of Q2, respectively.
FIGS. 2a to 2d are a series of diagrams showing the manufacturing sequence for the formation of a poly-via connecting the drain terminal of a load transistor, for example, the drain terminal 30 of Q4, with the gate terminal of a driver transistor, for example, the gate terminal 18 of Q1, in a conventional SRAM unit. First, it must be realized that the respective gate terminals of P-type thin film transistors Q3 and Q4 use the same common gate terminals 18 and 22 as that of the respective gate terminals of the transistors Q1 and Q2 respectively, and furthermore, that the channel, the source terminal and the gate terminal of each of the transistors Q3 and Q4 are formed on the same layer. Cross-sectional views, as shown in FIGS. 2a through 2d, are actually a portion of the connecting leg corresponding to one of the connecting legs such as 50 in the SRAM unit of FIG. 1.
First, as shown in FIG. 2a, a cross-sectional structure 100 of SRAM near the connecting leg, for example, one of the connecting legs 50 of FIG. 1, including an N-type silicon substrate 112 and having a previously formed P-well 114 is provided. Then, N-doped N.sup.+ source/drain regions 116 are formed inside the P-well 114 and are separated by a channel 118. Next, a first gate oxide layer 120 and a conducting layer 122 are sequentially formed above the P-well 114. The first gate oxide layer 120 can be, a silicon dioxide layer, for example, and the conducting layer 122 can be a polycide layer composed of a polysilicon layer and a silicide layer, for example.
Next in FIG. 2b, the conducting layer 122 is patterned, and then N-type ions 126 are doped to form an N.sup.+ gate 124 above the channel 118. The N.sup.+ source/drain regions 116 and the N.sup.+ gate 124 are equivalent to the source terminal 12, the drain terminal 20 and the gate terminal 18, respectively of transistor Q1 in FIG. 1. Thereafter, a second gate oxide layer 128 with a thickness of about 50 .ANG. to 400 .ANG., for example, is formed above the P-well, covering the N.sup.+ source/drain regions 116 and the N.sup.+ gate 124.
Subsequently, as shown in FIG. 2C, the second gate oxide layer 128 is defined and then etched to form a via 130 exposing part of the N.sup.+ gate 124. Next, a polysilicon layer 132 covering the second gate oxide layer 128 and filling the via 130 is formed.
Finally, in FIG. 2d, P-type ions 134 are doped into the polysilicon layer 132, forming P.sup.+ source/drain regions 136 of the thin film transistor, for example, like the drain terminal 30 of transistor Q4 in FIG. 1. Thereafter, an inter-layer dielectric (ILD) 138 layer is formed above the polysilicon layer 132, followed by subsequent processing necessary for the completion of SRAM.
However, the manufacturing method described above has a number of defects as follows:
1. In the conventional manufacturing process, the contact window opening is formed after the formation of a thin film transistor (TFT) gate oxide layer but before the formation of a TFT channel. Therefore the quality of the TFT gate oxide layer can be compromised as a result of pollutants from photolithographic processes, such as photoresist coating as well as subsequent etching. PA1 2. Since the enhancement mode NMOS transistor, Q1 for example, and the thin film transistor, Q3 for example, both use a common gate, resistance in the via at the contacting point where the N.sup.+ gate of an NMOS meets the P.sup.+ source/drain region of a TFT will be affected. PA1 3. For a similar reason as described in item number 2 above, because of the existence of a potential barrier in the N.sup.+ /P.sup.+ interface of a via, signal transferring operation through the circuit will be affected adversely.